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Configurations and Characteristics of Jfet

In the last post of Jfet, we learned some basic concepts of Jfet. In this post, we will be learning the configurations and characteristics of Jfet.

So as we saw in the BJT transistor that there were 3 configurations of BJT i.e. CB(Common Base), CE(Common Emitter), CC(Common Collector). But out of these 3, we preferred CE configuration and I hope you know the reason

Similar to BJT there are 3 configurations in Jfet as well and that are CG(Common Gate), Cs(Common Source), and CD(Common Drain). We will look at each and every configuration in a detailed way.

Jfet Configurations:-

1) Common Gate:-

In this configuration, the gate terminal of Jfet is kept common, or in other words, it is grounded.

 As you saw above in this configuration we got a signal in an amplified form. But still, we avoid using this configuration for normal use this is because it's internal input impedance(Zi) is very less. If you want to know what is the effect of the internal input impedance of any amplifier on signal then please do watch the video given below. Since it's internal input impedance is very less that's why we are not using it as an amplifier.


2) Common Drain:-

In this configuration, the drain terminal of Jfet is kept common, or in other words, it is grounded.

As you saw in the above figure that whatever the input signal we are giving to the input of Jfet the same signal is reflected at the output of the Jfet.So, in short, we can say that it is a buffer amplifier. Since it fails to amplify the input signal that's why we avoid using this configuration.

3) Common Source:-

In this configuration, the source terminal of Jfet is kept common, or in other words, it is grounded.

As you saw in the above figure that whatever signal we are providing to it, it is producing it's inverted but amplified form. So we can say that the output signal is 180 degrees out of phase to that of input in short it acts likes an invertor. Also, it's internal input impedance is high and output impedance is low. So due to these reasons, we are taking the Common Source configuration into practice.

Now, we will see the characteristics of Jfet. As you all know that in Bjt we had learned about the input and output characteristics of BJT and then we had tried to understand the working of BJT. Similarly, by looking at the characteristics of Jfet we will try to analyze the working of JFET. 

Characteristics of JFET:-

1) Transfer Characteristics of JFET:-

As we are studying this experiment, then we should first understand why we need to perform these experiments, and what is the significance of the transfer characteristics? I hope those who are reading this post are well acquainted with BJT, while understanding BJT we had done one experiment of input characteristics of BJT. In which we understood that the output current was dependent on input current i.e. Ib was directly proportional to Ic. 

Circuit Diagram:-

Similarly to check the relation between input and output parameters of JFET we are performing this experiment. So, similar to the input characteristics of BJT we are going to keep the output voltage constant i.e. Vds (Voltage between drain and source), and at the same time we will vary the input voltage i.e. Vgs(Gate to source voltage), at the end we will make some conclusions based on the graph. 
Note:- You can't vary Vgs positively if Vgs is positive then Jfet won't work properly since you are making both p-n junction diodes which are present in Jfet to operate in forward bias. So you have to vary Jfet negatively i.e. Vgs should vary from 0v to -6v or even less than -6v, it totally depends on which jfet you are using for the desired applications.
Based on the above steps we got the graph as shown below.

As you are seeing in the graph that if we are decreasing Vgs then the output current (Id) also decreases. In other words, let's say if the current Id=10mA when Vgs=0v. Now if we vary Vgs from 0v to -1v then the output current decreases i.e. when Vgs=-1v then Id=8mA. Similarly, if we keep on decreasing the voltage of Vgs then the output current Id also decreases, and at a certain value of Vgs= -Vgs(max) the current Id becomes zero(Id=0v). So in short we can say that the input voltage of JFET (Vgs) is directly proportional to the output current (Id). 
Vgs α Id
NOTE:- As I had explained in one of the posts i.e. rπ model of BJT that transfer word exists whenever we are working on one input and one output parameter for example here in this experiment we are plotting the graph of Vgs(input parameter) vs Id(output parameter). So as you can see your input voltage is controlling the output current therefore this characteristic is named as transfer characteristic of JFET.

2) Output or Drain Characteristics of JFET:-

Now as we are learning the output or drain characteristics of JFET, you can also compare it with the output characteristics of BJT. In output characteristics of BJT, we saw that when Vce increases then Ic also increases. Similarly, to check whether we get some relation between the output voltage(Vds) and output current(Id) of JFET, we are performing this experiment. 
Following steps are required while performing these experiments.
1) Set Vgs=Vgs(1) , Vgs(2) ,Vgs(3) ....Vgs=Vp
2) Set Vds=0v
Now let Vgs(1)=0v , Vgs(2)=-1v , Vgs(3)=-2v
Circuit Diagram:-
So as you can see in the above figure you have to move the knob of the variable resistor and set Vgs. Similarly, by moving Vdd you have to adjust Vds.
The procedure for carrying this experiment is that you have to set Vgs=Vgs(1) first then note 10 different values of Vds and Id by changing Vdd. Again change the value of Vgs=Vgs(2) and then note the 10 different values of Vds and Id. Repeat the procedure a few times and then plot Vds vs Id graph. The graph would be as shown below.
So from this graph, we can understand that as Vds increases Id also increases linearly after a certain point even if we increase Vds further the output current Id remains constant If we keep on increasing Vds then jfet will enter into the breakdown region and it will not work properly. 
The region up to which the Id increases linearly with Vds is known as the ohmic region while the region after which Id remains constant even after increasing Vds is known as the saturation region. I'm not explaining the concept of Dc load line and q-point in this post as I had explained these concepts in a detailed way in the post on biasing and the need for biasing transistors
So in short by learning both the characteristics we can say that the output current Id is dependent on Vgs and Vds as well. Thus we can say that Id α Vgs, and Id α Vds

Now you would be confused that in output characteristics of BJT the saturation region was giving some different result (switch which was working in 'on' condition) but here we are calling the linear region of jfet as saturation while some authors also name it as an active region. So please don't get confused, BJT and JFET both are different concepts. 
So I hope you understood this post 


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