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Ac Analysis of JFET

Until now we had covered almost all of the topics of dc analysis of JFET. If you want to start with Dc analysis of JFET, I recommend you start with this post on JFET:- Junction Field Effect Transistor. So in this post, we are going to study ac analysis of JFET.
Before starting with the post I want to give you a brief idea that what concepts we are going to learn by the end of this post. 
1) Ac Analysis of CS-amplifier
2) Ac Analysis of CG-amplifier
3) Different parameters and it's importance while designing an amplifier. 
We will try to understand it's working by using bypass and unbypassed capacitors.

1) Ac Analysis of CS Amplifier:-
Here I'm considering a self-bias circuit you can also consider voltage divider bias and according to the superposition theorem during ac analysis, all the dc sources are grounded.
(Remember that during Ac-analysis capacitors are replaced by short-circuit and during Dc-analysis capacitors are replaced by open-circuit.)

a) Calculation of Input Impedance( Rin = Zin) and input voltage (Vin):-
So let's go to the analysis part we know that the gate and source terminals are like reverse-biased p-n junction diode. Since gate-source voltage acts like reverse bias p-n junction diode, current through the gate-source terminal is zero, which means gate-source voltage offers high or infinite resistance. Therefore the input impedance of JFET from the figure given below is Rin = Zin = Rg
For calculation of Vin
Vin = Vgs + Voltage drop across resistor Rs
Vin =  Vgs + Id * Rs
therefore Vin = Vgs + gm*Vgs*Rs

b) Concept of Drain current, output resistance, and output voltage:- 
Now, from the last post we studied that gm = ΔVgs / ΔId but now as we had biased JFET, therefore, there won't be any change in drain current with respect to temperature thus we can neglect the change or the delta(Δ) symbol. 
Therefore we can say that Id = gm * Vgs
Since the current Id is moving from drain to source therefore it is represented as shown below.
Now, you might be thinking that why I had connected resistance rd in parallel with Id so for that I hope you know that the internal resistance of an ideal current source is infinite but here the current Id is finite therefore the practical value of rd is around 50kΩ. 
Rout = Zout = rd || Rd
Vout = - Id * Rout = - gm * Vgs * (rd || Rd)
Here, a negative sign for Vout indicates that the current Id is moving in the opposite direction.
NOTE:-rd>>Rd thus current through rd=0A therefore the voltage drop across resistance rd = 0v (rd || Rd = Rd).  

Ac analysis of CS amplifier:-
Now as I had explained to you in BJT as an amplifier that the for designing an amplifier 4 parameters plays a very significant role that is Input impedance(Zi)Output Impedance(Zo), Voltage gain(Av), and Current gain(Ai) but we neglect current gain because JFET is voltage-controlled current source.

# All the parameters of CS-Amplifier:-
Input Impedance (Zi) = Rg
Output Impedance (Zo) = Rd || rd
Input voltage (Vin) = Vgs + Id*Rs = Vgs + gm*Vgs*Rs
Output Voltage (Vout) = Id*Rd = gm*Vgs*(Rd || rd)
Voltage gain (Av) = Vout / Vin = gm*(Rd || rd) / 1 + gm*Rs

Now, if we are using a bypass capacitor that is if we are connecting a capacitor in parallel with source resistance(Rs) then a capacitor will pass the Ac signal and block the dc and there are many more reasons to connect the capacitor in parallel with Rs. I won't be explaining those reasons in this post because I had explained all those reasons in great depth in the post of the Common Emitter Amplifier.
So the whole circuit will be the same but Rs is replaced by a short circuit and the circuit can be shown as below.
Now it's your responsibility to calculate all of the above-mentioned parameters when we connect the capacitor at the source terminal.

2) Ac Analysis of CG Amplifier:-
Now, we will see the Common gate configuration of JFET but before that, we should know that why we are using this configuration and the reason I had explained in great depth in the post on Configuration and Characteristics of JFET.

Now we will analyze the key parameters for CG configuration
1) Input Impedance of JFET (Rin = Zi):-
Now, to calculate or to find the input impedance of JFET  we need to apply KCL at the source terminal
image of calculation of input impedance.
Therefore, input impedance :- Ri = Rs || (1/gm)

2) Voltage gain (Av):- 
We know that Av = Vout / Vin

a) For calculation of input voltage (Vin):-
Now, from the above figure when we apply KVL to the source terminal we get
Vin - Vs = 0
therefore Vin = Vs.....(1)
Also,
 Vgs = Vg - Vs
therefore Vgs = -Vs....(2)......(Since gate terminal is grounded)
thus from equation (1) and (2), we can say that
Vin = - Vgs

b) To calculate Vout just see the figure given below:-
Vout = -gm*Vgs*(Rd || RL)
Therefore Av = Vout / Vin
Av = gm*(Rd || RL)

3) Output Impedance (Ro):-
From the above figure, you can easily see that Ro = Zo = Rd || RL

# All the parameters of CG-Amplifier:-
Input Impedance (Zi) = Rs || (1/gm)
Output Impedance (Zo) = Rd || RL
Input voltage (Vin) = Vin = - Vgs
Output Voltage (Vout) =  -gm*Vgs*(Rd || RL)
Voltage gain (Av) = Vout / Vin = gm*(Rd || RL)

I hope you understood all the concepts that I had explained in this post if you are loving my posts then please do subscribe to my site by clicking on the notification bell.

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